PROGRAMMING MODEL
								7				0
								A								ACCUMULATOR
								7				0
								Y								INDEX REGISTER Y
								7				0
								X								INDEX REGISTER X
15								7				0
PCH								PCL								PROGRAM COUNTER
								7				0
						01		S								STACK POINTER
								7				0
								N	V	-	B	D	I	Z	C	PROCESSOR STATUS REGISTER "P"
								NEGATIVE	OVERFLOW		BREAK COMMAND	DECIMAL MODE	INTERRUPT DISABLE	ZERO	CARRY

INSTRUCTION NOTATION
A	Accumulator	FIGURE 1. ASL – SHIFT ONE BIT LEFT C ← 7 6 5 4 3 2 1 0 ← 0 FIGURE 2. LSR – SHIFT ONE BIT RIGHT 0 → 7 6 5 4 3 2 1 0 → C FIGURE 3. ROL – ROTATE ONE BIT LEFT C ← 7 6 5 4 3 2 1 0 ← C FIGURE 4. ROR – ROTATE ONE BIT RIGHT C → 7 6 5 4 3 2 1 0 → C NOTE 1. BIT – TEST BITS Bit 6 and 7 are transfered to the status register. If the result of A ∧ M is zero then Z=1, else Z=0.
X, Y	Index Registers
M	Memory
C	Borrow
P	Processor Status Register
S	Stack Pointer
✓	Change
–	No Change
+	Add
∧	Logical AND
-	Subtract
⊻	Logical Exclusive OR
↑	Transfer From Stack
↓	Transfer To Stack
→	Transfer To
←	Transfer To
∨	Logical OR
PC	Program Counter
PCH	Program Counter High
PCL	Program Counter Low
Oper	Operand
#	Immediate Addressing Mode

Name Description	Operation	Addressing Mode	Assembly Language Form	HEX OP Code	No. Bytes	"P" Status Reg. N Z C I D V
ADC
Add memory to accumulator with carry	A + M + C → A	Immediate Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	ADC #Oper ADC Oper ADC Oper,X ADC Oper ADC Oper,X ADC Oper,Y ADC (Oper,X) ADC (Oper),Y	69 65 75 6D 7D 79 61 71	2 2 2 3 3 3 2 2	✓ ✓ ✓ – – ✓
AND
"AND" memory with accumulator	A ∧ M → A	Immediate Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	AND #Oper AND Oper AND Oper,X AND Oper AND Oper,X AND Oper,Y AND (Oper,X) AND (Oper),Y	29 25 35 2D 3D 39 21 31	2 2 2 3 3 3 2 2	✓ ✓ – – – –
ASL
Shift left one bit (Memory or Accumulator)	(See Figure 1)	Accumulator Zero Page Zero Page,X Absolute Absolute,X	ASL A ASL Oper ASL Oper,X ASL Oper ASL Oper,X	0A 06 16 0E 1E	1 2 2 3 3	✓ ✓ ✓ – – –
BCC
Branch on carry clear	Branch on C=0	Relative	BCC Oper	90	2	– – – – – –
BCS
Branch on carry set	Branch on C=1	Relative	BCS Oper	B0	2	– – – – – –
BEQ
Branch on result zero	Branch on Z=1	Relative	BEQ Oper	F0	2	– – – – – –
BIT
Test bits in memory with accumulator	A ∧ M M7 → N M6 → V	Zero Page Absolute	BIT Oper BIT Oper	24 2C	2 3	M7 ✓ – – – M6
BMI
Branch on result minus	Branch on N=1	Relative	BMI Oper	30	2	– – – – – –
BNE
Branch on result not zero	Branch on Z=0	Relative	BNE Oper	D0	2	– – – – – –
BPL
Branch on result plus	Branch on N=0	Relative	BPL Oper	10	2	– – – – – –
BRK
Force break interrupt	Forced Interrupt PC + 2 ↓ P ↓	Implied	BRK	00	1	– – – 1 – –
BVC
Branch on overflow clear	Branch on V=0	Relative	BVC Oper	50	2	– – – – – –

Name Description	Operation	Addressing Mode	Assembly Language Form	HEX OP Code	No. Bytes	"P" Status Reg. N Z C I D V
BVS
Branch on overflow set	Branch on V=1	Relative	BVS Oper	70	2	– – – – – –
CLC
Clear carry flag	0 → C	Implied	CLC	18	1	– – 0 – – –
CLD
Clear decimal mode	0 → D	Implied	CLD	D8	1	– – – – 0 –
CLI
Clear interrupt disable	0 → I	Implied	CLI	58	1	– – – 0 – –
CLV
Clear overflow flag	0 → V	Implied	CLV	B8	1	– – – – – 0
CMP
Compare memory and accumulator	A - M	Immediate Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	CMP #Oper CMP Oper CMP Oper,X CMP Oper CMP Oper,X CMP Oper,Y CMP (Oper,X) CMP (Oper),Y	C9 C5 D5 CD DD D9 C1 D1	2 2 2 3 3 3 2 2	✓ ✓ ✓ – – –
CPX
Compare memory and index X	X - M	Immediate Zero Page Absolute	CPX #Oper CPX Oper CPX Oper	E0 E4 EC	2 2 3	✓ ✓ ✓ – – –
CPY
Compare memory and index Y	Y - M	Immediate Zero Page Absolute	CPY #Oper CPY Oper CPY Oper	C0 C4 CC	2 2 3	✓ ✓ ✓ – – –
DEC
Decrement memory by one	M - 1 → M	Zero Page Zero Page,X Absolute Absolute,X	DEC Oper DEC Oper,X DEC Oper DEC Oper,X	C6 D6 CE DE	2 2 3 3	✓ ✓ – – – –
DEX
Decrement index X by one	X - 1 → X	Implied	DEX	CA	1	✓ ✓ – – – –
DEY
Decrement index Y by one	Y - 1 → Y	Implied	DEY	88	1	✓ ✓ – – – –
EOR
"Exclusive OR" memory with accumulator	A ⊻ M → A	Immediate Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	EOR #Oper EOR Oper EOR Oper,X EOR Oper EOR Oper,X EOR Oper,Y EOR (Oper,X) EOR (Oper),Y	49 45 55 4D 5D 59 41 51	2 2 2 3 3 3 2 2	✓ ✓ – – – –

Name Description	Operation	Addressing Mode	Assembly Language Form	HEX OP Code	No. Bytes	"P" Status Reg. N Z C I D V
INC
Increment memory by one	M + 1 → M	Zero Page Zero Page,X Absolute Absolute,X	INC Oper INC Oper,X INC Oper INC Oper,X	E6 F6 EE FE	2 2 3 3	✓ ✓ – – – –
INX
Increment index X by one	X + 1 → X	Implied	INX	E8	1	✓ ✓ – – – –
INY
Increment index Y by one	Y + 1 → Y	Implied	INY	C8	1	✓ ✓ – – – –
JMP
Jump to new location	PC + 1 → PCL PC + 2 → PCH	Absolute (Indirect)	JMP Oper JMP (Oper)	4C 6C	3 3	– – – – – –
JSR
Jump to new location saving return address	PC + 2 ↓ PC + 1 → PCL PC + 2 → PCH	Absolute	JSR Oper	20	3	– – – – – –
LDA
Load accumulator with memory	M → A	Immediate Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	LDA #Oper LDA Oper LDA Oper,X LDA Oper LDA Oper,X LDA Oper,Y LDA (Oper,X) LDA (Oper),Y	A9 A5 B5 AD BD B9 A1 B1	2 2 2 3 3 3 2 2	✓ ✓ – – – –
LDX
Load index X with memory	M → X	Immediate Zero Page Zero Page,Y Absolute Absolute,Y	LDX #Oper LDX Oper LDX Oper,Y LDX Oper LDX Oper,Y	A2 A6 B6 AE BE	2 2 2 3 3	✓ ✓ – – – –
LDY
Load index Y with memory	M → Y	Immediate Zero Page Zero Page,X Absolute Absolute,X	LDY #Oper LDY Oper LDY Oper,X LDY Oper LDY Oper,X	A0 A4 B4 AC BC	2 2 2 3 3	✓ ✓ – – – –
LSR
Shift right one bit (memory or accumulator)	(See Figure 2)	Accumulator Zero Page Zero Page,X Absolute Absolute,X	LSR A LSR Oper LSR Oper,X LSR Oper LSR Oper,X	4A 46 56 4E 5E	1 2 2 3 3	0 ✓ ✓ – – –
NOP
No operation	No operation	Implied	NOP	EA	1	– – – – – –

Name Description	Operation	Addressing Mode	Assembly Language Form	HEX OP Code	No. Bytes	"P" Status Reg. N Z C I D V
ORA
"OR" memory with accumulator	A ∨ M → A	Immediate Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	ORA #Oper ORA Oper ORA Oper,X ORA Oper ORA Oper,X ORA Oper,Y ORA (Oper,X) ORA (Oper),Y	09 05 15 0D 1D 19 01 11	2 2 2 3 3 3 2 2	✓ ✓ – – – –
PHA
Push accumulator on stack	A ↓	Implied	PHA	48	1	– – – – – –
PHP
Push processor status on stack	P ↓	Implied	PHP	08	1	– – – – – –
PLA
Pull accumulator from stack	A ↑	Implied	PLA	68	1	✓ ✓ – – – –
PLP
Pull processor status from stack	P ↑	Implied	PLP	28	1	From Stack
ROL
Rotate one bit left (memory or accumulator)	(See Figure 3)	Accumulator Zero Page Zero Page,X Absolute Absolute,X	ROL A ROL Oper ROL Oper,X ROL Oper ROL Oper,X	2A 26 36 2E 3E	1 2 2 3 3	✓ ✓ ✓ – – –
ROR
Rotate one bit right (memory or accumulator)	(See Figure 4)	Accumulator Zero Page Zero Page,X Absolute Absolute,X	ROR A ROR Oper ROR Oper,X ROR Oper ROR Oper,X	6A 66 76 6E 7E	1 2 2 3 3	✓ ✓ ✓ – – –
RTI
Return from interrupt	P ↑ PC ↑	Implied	RTI	40	1	From Stack
RTS
Return from subroutine	PC ↑ PC + 1 → PC	Implied	RTS	60	1	– – – – – –
SBC
Subtract memory from accumulator with borrow	A - M - C → A	Immediate Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	SBC #Oper SBC Oper SBC Oper,X SBC Oper SBC Oper,X SBC Oper,Y SBC (Oper,X) SBC (Oper),Y	E9 E5 F5 ED FD F9 E1 F1	2 2 2 3 3 3 2 2	✓ ✓ ✓ – – ✓

Name Description	Operation	Addressing Mode	Assembly Language Form	HEX OP Code	No. Bytes	"P" Status Reg. N Z C I D V
SEC
Set carry flag	1 → C	Implied	SEC	38	1	– – 1 – – –
SED
Set decimal mode	1 → D	Implied	SED	F8	1	– – – – 1 –
SEI
Set interrupt disable	1 → I	Implied	SEI	78	1	– – – 1 – –
STA
Store accumulator in memory	A → M	Zero Page Zero Page,X Absolute Absolute,X Absolute,Y (Indirect,X) (Indirect),Y	STA Oper STA Oper,X STA Oper STA Oper,X STA Oper,Y STA (Oper,X) STA (Oper),Y	85 95 8D 9D 99 81 91	2 2 3 3 3 2 2	– – – – – –
STX
Store index X in memory	X → M	Zero Page Zero Page,Y Absolute	STX Oper STX Oper,Y STX Oper	86 96 8E	2 2 3	– – – – – –
STY
Store index Y in memory	Y → M	Zero Page Zero Page,X Absolute	STY Oper STY Oper,X STY Oper	84 94 8C	2 2 3	– – – – – –
TAX
Transfer accumulator to index X	A → X	Implied	TAX	AA	1	✓ ✓ – – – –
TAY
Transfer accumulator to index Y	A → Y	Implied	TAY	A8	1	✓ ✓ – – – –
TSX
Transfer stack pointer to index X	S → X	Implied	TSX	BA	1	✓ ✓ – – – –
TXA
Transfer index X to accumulator	X → A	Implied	TXA	8A	1	✓ ✓ – – – –
TXS
Transfer index X to stack pointer	X → S	Implied	TXS	9A	1	– – – – – –
TYA
Transfer index Y to accumulator	Y → A	Implied	TYA	98	1	✓ ✓ – – – –

HEX OPERATION CODES
00	BRK		40	RTI		80			C0	CPY	Immediate
01	ORA	(Indirect,X)	41	EOR	(Indirect,X)	81	STA	(Indirect,X)	C1	CMP	(Indirect,X)
02			42			82			C2
03			43			83			C3
04			44			84	STY	Zero Page	C4	CPY	Zero Page
05	ORA	Zero Page	45	EOR	Zero Page	85	STA	Zero Page	C5	CMP	Zero Page
06	ASL	Zero Page	46	LSR	Zero Page	86	STX	Zero Page	C6	DEC	Zero Page
07			47			87			C7
08	PHP		48	PHA		88	DEY		C8	INY
09	ORA	Immediate	49	EOR	Immediate	89			C9	CMP	Immediate
0A	ASL	Accumulator	4A	LSR	Accumulator	8A	TXA		CA	DEX
0B			4B			8B			CB
0C			4C	JMP	Absolute	8C	STY	Absolute	CC	CPY	Absolute
0D	ORA	Absolute	4D	EOR	Absolute	8D	STA	Absolute	CD	CMP	Absolute
0E	ASL	Absolute	4E	LSR	Absolute	8E	STX	Absolute	CE	DEC	Absolute
0F			4F			8F			CF
10	BPL		50	BVC		90	BCC		D0	BNE
11	ORA	(Indirect),Y	51	EOR	(Indirect),Y	91	STA	(Indirect),Y	D1	CMP	(Indirect),Y
12			52			92			D2
13			53			93			D3
14			54			94	STY	Zero Page,X	D4
15	ORA	Zero Page,X	55	EOR	Zero Page,X	95	STA	Zero Page,X	D5	CMP	Zero Page,X
16	ASL	Zero Page,X	56	LSR	Zero Page,X	96	STX	Zero Page,Y	D6	DEC	Zero Page,X
17			57			97			D7
18	CLC		58	CLI		98	TYA		D8	CLD
19	ORA	Absolute,Y	59	EOR	Absolute,Y	99	STA	Absolute,Y	D9	CMP	Absolute,Y
1A			5A			9A	TXS		DA
1B			5B			9B			DB
1C			5C			9C			DC
1D	ORA	Absolute,X	5D	EOR	Absolute,X	9D	STA	Absolute,X	DD	CMP	Absolute,X
1E	ASL	Absolute,X	5E	LSR	Absolute,X	9E			DE	DEC	Absolute,X
1F			5F			9F			DF
20	JSR	Absolute	60	RTS		A0	LDY	Immediate	E0	CPX	Immediate
21	AND	(Indirect,X)	61	ADC	(Indirect,X)	A1	LDA	(Indirect,X)	E1	SBC	(Indirect,X)
22			62			A2	LDX	Immediate	E2
23			63			A3			E3
24	BIT	Zero Page	64			A4	LDY	Zero Page	E4	CPX	Zero Page
25	AND	Zero Page	65	ADC	Zero Page	A5	LDA	Zero Page	E5	SBC	Zero Page
26	ROL	Zero Page	66	ROR	Zero Page	A6	LDX	Zero Page	E6	INC	Zero Page
27			67			A7			E7
28	PLP		68	PLA		A8	TAY		E8	INX
29	AND	Immediate	69	ADC	Immediate	A9	LDA	Immediate	E9	SBC	Immediate
2A	ROL	Accumulator	6A	ROR	Accumulator	AA	TAX		EA	NOP
2B			6B			AB			EB
2C	BIT	Absolute	6C	JMP	(Indirect)	AC	LDY	Absolute	EC	CPX	Absolute
2D	AND	Absolute	6D	ADC	Absolute	AD	LDA	Absolute	ED	SBC	Absolute
2E	ROL	Absolute	6E	ROR	Absolute	AE	LDX	Absolute	EE	INC	Absolute
2F			6F			AF			EF
30	BMI		70	BVS		B0	BCS		F0	BEQ
31	AND	(Indirect),Y	71	ADC	(Indirect),Y	B1	LDA	(Indirect),Y	F1	SBC	(Indirect),Y
32			72			B2			F2
33			73			B3			F3
34			74			B4	LDY	Zero Page,X	F4
35	AND	Zero Page,X	75	ADC	Zero Page,X	B5	LDA	Zero Page,X	F5	SBC	Zero Page,X
36	ROL	Zero Page,X	76	ROR	Zero Page,X	B6	LDX	Zero Page,Y	F6	INC	Zero Page,X
37			77			B7			F7
38	SEC		78	SEI		B8	CLV		F8	SED
39	AND	Absolute,Y	79	ADC	Absolute,Y	B9	LDA	Absolute,Y	F9	SBC	Absolute,Y
3A			7A			BA	TSX		FA
3B			7B			BB			FB
3C			7C			BC	LDY	Absolute,X	FC
3D	AND	Absolute,X	7D	ADC	Absolute,X	BD	LDA	Absolute,X	FD	SBC	Absolute,X
3E	ROL	Absolute,X	7E	ROR	Absolute,X	BE	LDX	Absolute,Y	FE	INC	Absolute,X
3F			7F			BF			FF