MCS6500 - Summary of Single-Cycle Execution

APPENDIX A

SUMMARY OF SINGLE-CYCLE EXECUTION

This section contains an outline of the data on both the address bus and the data bus for each cycle of the various processor instructions. It tells the system designer exactly what to expect while single-cycling through a program.

Note that the processor will not stop in any cycle where R/W is a 0 (WRITE cycle). Instead, it will go right into the next READ cycle and stop there. For this reason, some instructions may appear to be shorter than indicated here.

All Instructions begin with T0 and the fetch of the OP CODE and continue through the required number of cycles until the next T0 and the fetch of the next OP CODE.

While the basic terminology used in this appendix is discussed in the Programming Manual, it has been defined below for ease of reference while studying Single-Cycle Execution.

OP CODE: The first byte of the instruction containing the operator and mode of address.
OPERAND: The data on which the operation specified In the OP CODE is performed.
BASE ADDRESS: The address in Indexed addressing modes which specifies the location in memory to which indexing is referenced. The high-order byte of the base address (AB08 to AB15) is BAH (Base Address High) and the low-order byte of the base address (AB00 to AB07) is BAL (Base Address Low).
EFFECTIVE ADDRESS: The destination in memory in which data are to be found. The effective address may be loaded directly as in the case of Page Zero and Absolute Addressing or may be calculated as in Indexing operations. The high-order byte of the effective address (AB08 to AB15) is ADH and the low-order byte of the effective address (AB00 to AB07) is ADL.
INDIRECT ADDRESS: The address found in the operand of instructions utilizing (Indirect),Y which contains the low-order byte of the base address. IAH and IAL represent the high- and low-order bytes.
JUMP ADDRESS: The value to be loaded into Program Counter as a result of a Jump instruction.

A. 1. SINGLE-BYTE INSTRUCTIONS

ASL	DEX	ROL	TAX
CLC	DEY	ROR	TAY
CLD	INX	SEC	TSX
CLI	INY	SED	TXA
CLV	LSR	SEI	TXS
	NOP		TYA

These single-byte instructions require two cycles to execute. During the second cycle the address of the next instruction in program sequence will be placed on the address bus. However, the OP CODE which appears on the data bus during the second cycle will be ignored. This same instruction will be fetched on the following cycle, at which time it will be decoded and executed. The ASL, LSR, ROL and ROR instructions apply to the accumulator mode of address.

A. 1.1 Implied Addressing (2 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	OP CODE (Discarded)	1
T0	PC + 1	OP CODE	1	Next Instruction

A. 2. INTERNAL EXECUTION ON MEMORY DATA

ADC	CMP	EOR	LDY
AND	CPX	LDA	ORA
BIT	CPY	LDX	SBC

The instructions listed above will execute by performing operations inside the microprocessor using data fetched from the effective address. This total operation requires three steps. The first step (one cycle) is the OP CODE fetch. The second (zero to four cycles) Is the calculation of an effective address. The final step is the fetching of the data from the effective address. Execution of the instruction takes place during the fetching and decoding of the next instruction.

A. 2.1. Immediate Addressing (2 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	Data	1	Fetch Data
T0	PC + 2	OP CODE	1	Next Instruction

A. 2.2. Zero Page Addressing (3 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Effective Address
T2	00, ADL	Data	1	Fetch Data
T0	PC + 2	OP CODE	1	Next Instruction

A. 2.3. Absolute Addressing (4 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Low-Order Effective Address Byte
T2	PC + 2	ADH	1	Fetch High-Order Effective Address Byte
T3	ADH, ADL	Data	1	Fetch Data
T0	PC + 3	OP CODE	1	Next Instruction

A. 2.4. Indirect, X Addressing (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Page Zero Base Address
T2	00, BAL	Data (Discarded)	1
T3	00, BAL + X	ADL	1	Fetch Low-Order Byte of Effective Address
T4	00, BAL + X + 1	ADH	1	Fetch High-Order Byte of Effective Address
T5	ADH, ADL	Data	1	Fetch Data
T0	PC + 2	OP CODE	1	Next Instruction

A. 2.5. Absolute, X or Absolute, Y Addressing (4 or 5 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Low-Order Byte of Base Address
T2	PC + 2	BAH	1	Fetch High-Order Byte of Base Address
T3	ADL: BAL + Index ADH: BAH + C	Data^a	1	Fetch Data (No Page Crossing) Carry is 0 or 1 as Required from Previous Add Operation
T4^a	ADL: BAL + Index ADH: BAH + 1	Data	1	Fetch Data from Next Page
T0	PC + 3	OP CODE	1	Next Instruction

If the page boundary is crossed in the indexing operation, the data fetched in T3 is ignored. If page boundary is not crossed, the T4 cycle is bypassed.

A. 2.6. Zero Page, X or Zero Page, Y Addressing Modes (4 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Page Zero Base Address
T2	00, BAL	Data (Discarded)	1
T3	00, BAL + Index	Data	1	Fetch Data (No Page Crossing)
T0	PC + 2	OP CODE	1	Next Instruction

A. 2.7. Indirect, Y Addressing Mode (5 or 6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	IAL	1	Fetch Page Zero Indirect Address
T2	00, IAL	BAL	1	Fetch Low-Order Byte of Base Address
T3	00, IAL + 1	BAH	1	Fetch High-Order Byte of Base Address
T4	ADL: BAL + Y ADH: BAH + C	Data^a	1	Fetch Data from Same Page Carry is 0 or 1 as Required from Previous Add Operation
T5^a	ADL: BAL + Y ADH: BAH + 1	Data	1	Fetch Data from Next Page
T0	PC + 2	OP CODE	1	Next Instruction

If the page boundary is crossed in the indexing operation, the data fetched in T4 is ignored. If page boundary is not crossed, the T5 cycle is bypassed.

A. 3. STORE OPERATAIONS

STA
STX
STY

The specific steps taken in the Store Operations are very similar to those taken in the previous group (internal execution on memory data). However, in the Store Operation, the fetch of data is replaced by a WRITE (R/W = 0) cycle. No overlapping occurs and no shortening of the instruction time occurs on indexing operations.

A. 3.1. Zero Page Addressing (3 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Zero Page Effective Address
T2	00, ADL	Data	0	Write Internal Register to Memory
T0	PC + 2	OP CODE	1	Next Instruction

A. 3.2. Absolute Addressing (4 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Low-Order Byte of Effective Address
T2	PC + 2	ADH	1	Fetch High-Order Byte of Effective Address
T3	ADH, ADL	Data	0	Write Internal Register to Memory
T0	PC + 3	OP CODE	1	Next Instruction

A. 3.3. Indirect, X Addressing (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Page Zero Base Address
T2	00, BAL	Data (Discarded)	1
T3	00, BAL + X	ADL	1	Fetch Low-Order Byte of Effective Address
T4	00, BAL + X + 1	ADH	1	Fetch High-Order Byte of Effective Address
T5	ADH, ADL	Data	0	Write Internal Register to Memory
T0	PC + 2	OP CODE	1	Next Instruction

A. 3.4. Absolute, X or Absolute, Y Addressing (5 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Low-Order Byte of Base Address
T2	PC + 2	BAH	1	Fetch High-Order Byte of Base Address
T3	ADL: BAL + Index ADH: BAH + C	Data (Discarded)	1
T4	ADH, ADL	Data	0	Write Internal Register to Memory
T0	PC + 3	OP CODE	1	Next Instruction

A. 3.5. Zero Page, X or Zero Page, Y Addressing Modes (4 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Page Zero Base Address
T2	00, BAL	Data (Discarded)	1
T3	ADL: BAL + Index	Data	0	Write Internal Register to Memory
T0	PC + 2	OP CODE	1	Next Instruction

A. 3.6. Indirect, Y Addressing Mode (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	IAL	1	Fetch Page Zero Indirect Address
T2	00, IAL	BAL	1	Fetch Low-Order Byte of Base Address
T3	00, IAL + 1	BAH	1	Fetch High-Order Byte of Base Address
T4	ADL: BAL + Y ADH: BAH	Data (Discarded)	1
T5	ADH, ADL	Data	0	Write Internal Register to Memory
T0	PC + 2	OP CODE	1	Next Instruction

A. 4. READ -- MODIFY -- WRITE OPERATAIONS

ASL	LSR
DEC	ROL
INC	ROR

The Read -- Modify -- Write operations involve the loading of operands from the operand address, modification of the operand and the resulting modified data being stored in the original location.

A. 4.1. Zero Page Addressing (5 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Page Zero Effective Address
T2	00, ADL	Data	1	Fetch Data
T3	00, ADL	Data	0
T4	00, ADL	Modified Data	0	Write Modified Data Back into Memory
T0	PC + 2	OP CODE	1	Next Instruction

A. 4.2. Absolute Addressing (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Low-Order Byte of Effective Address
T2	PC + 2	ADH	1	Fetch High-Order Byte of Effective Address
T3	ADH, ADL	Data	1	Fetch Data
T4	ADH, ADL	Data	0
T5	ADH, ADL	Modified Data	0	Write Modified Data Back into Memory
T0	PC + 3	OP CODE	1	Next Instruction

A. 4.3. Zero Page, X Addressing (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Page Zero Base Address
T2	00, BAL	Data (Discarded)	1
T3	ADL: BAL + X (w/o Carry)	Data	1	Fetch Data
T4	ADL: BAL + X (w/o Carry)	Data	0
T5	ADL: BAL + X (w/o Carry)	Modified Data	0	Write Modified Data Back into Memory
T0	PC + 2	OP CODE	1	Next Instruction

A. 4.4. Absolute, X Addressing (7 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	BAL	1	Fetch Low-Order Byte of Base Address
T2	PC + 2	BAH	1	Fetch High-Order Byte of Base Address
T3	ADL: BAL + X ADH: BAH + C	Data (Discarded)	1
T4	ADL: BAL + X ADH: BAH + C	Data	1	Fetch Data
T5	ADH, ADL	Data	0
T6	ADH, ADL	Modified Data	0	Write Modified Data Back into Memory
T0	PC + 3	OP CODE	1	Next Instruction

A. 5. MISCELLANEOUS OPERATIONS

BCC	BRK	PHA
BCS	BVC	PHP
BEQ	BVS	PLA
BMI		PLP
BNE	JMP	RTI
BPL	JSR	RTS

A. 5.1. Push Operations -- PHP, PHA (3 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	OP CODE (Discarded)	1
T2	Stack Pointer	Data	0	Write Internal Register into Stack
T0	PC + 1	OP CODE	1	Next Instruction

A. 5.2. Pull Operations -- PLP, PLA (4 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	OP CODE (Discarded)	1
T2	Stack Pointer	Data (Discarded)	1
T3	Stack Pointer + 1	Data	1	Fetch Data from Stack
T0	PC + 1	OP CODE	1	Next Instruction

A. 5.3. Jump to Subroutine -- JSR (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Low-Order Byte of Subroutine Address
T2	Stack Pointer	Data (Discarded)	1
T3	Stack Pointer	PCH	0	Push High-Order Byte of Program Counter to Stack
T4	Stack Pointer - 1	PCL	0	Push Low-Order Byte of Program Counter to Stack
T5	PC + 2	ADH	1	Fetch High-Order Byte of Subroutine Address
T0	Subroutine Address (ADH, ADL)	OP CODE	1	Next Instruction

A. 5.4. Break Operation -- (Hardware Interrupt)-BRK (7 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch BRK OP CODE (or Force BRK)
T1	PC + 1 (PC on Hardware Interrupt)	Data (Discarded)	1
T2	Stack Pointer	PCH	0	Push High-Order Byte of Program Counter to Stack
T3	Stack Pointer - 1	PCL	0	Push Low-Order Byte of Program Counter to Stack
T4	Stack Pointer - 2	P	0	Push Status Register to Stack
T5	FFFE (NMI-FFFA) (RES-FFFC)	ADL	1	Fetch Low-Order Byte of Interrupt Vector
T6	FFFF (NMI-FFFB) (RES-FFFD)	ADH	1	Fetch High-Order Byte of Interrupt Vector
T0	Interrupt Vector (ADH, ADL)	OP CODE	1	Next Instruction

A. 5.5. Return from Interrupt -- RTI (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	Data (Discarded)	1
T2	Stack Pointer	Data (Discarded)	1
T3	Stack Pointer + 1	Data	1	Pull P from Stack
T4	Stack Pointer + 2	Data	1	Pull PCL from Stack
T5	Stack Pointer + 3	Data	1	Pull PCH from Stack
T0	PCH, PCL	OP CODE	1	Next Instruction

A. 5.6. Jump Operation -- JMP

A. 5.6.1 Absolute Addressing Mode (3 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	ADL	1	Fetch Low-Order Byte of Jump Address
T2	PC + 2	ADH	1	Fetch High-Order Byte of Jump Address
T0	ADH, ADL	OP CODE	1	Next Instruction

A. 5.6.2 Indirect Addressing Mode (5 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	IAL	1	Fetch Low-Order Byte of Indirect Address
T2	PC + 2	IAH	1	Fetch High-Order Byte of Indirect Address
T3	IAH, IAL	ADL	1	Fetch Low-Order Byte of Jump Address
T4	IAH, IAL + 1	ADH	1	Fetch High-Order Byte of Jump Address
T0	ADH, ADL	OP CODE	1	Next Instruction

A. 5.7. Return from Subroutine -- RTS (6 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	Data (Discarded)	1
T2	Stack Pointer	Data (Discarded)	1
T3	Stack Pointer + 1	PCL	1	Pull PCL from Stack
T4	Stack Pointer + 2	PCH	1	Pull PCH from Stack
T5	PCH, PCL (from Stack)	Data (Discarded)	1
T0	PCH, PCL + 1	OP CODE	1	Next Instruction

A. 5.8. Branch Operation -- BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS (2, 3, or 4 Cycles)

Tn	Address Bus	Data Bus	R/W	Comments
T0	PC	OP CODE	1	Fetch OP CODE
T1	PC + 1	Offset	1	Fetch Branch Offest
T2^a	PC + 2 + Offset (w/o Carry)	OP CODE	1	Offset Added to Program Counter
T3^b	PC + 2 + Offset (with Carry)	OP CODE	1	Carry Added

Skip if branch not taken.
Skip if branch not taken; skip if branch operation does not cross page boundary.

ASL	DEX	ROL	TAX
CLC	DEY	ROR	TAY
CLD	INX	SEC	TSX
CLI	INY	SED	TXA
CLV	LSR	SEI	TXS
	NOP		TYA

ASL	DEX	ROL	TAX
CLC	DEY	ROR	TAY
CLD	INX	SEC	TSX
CLI	INY	SED	TXA
CLV	LSR	SEI	TXS
	NOP		TYA

MCS6500 Microcomputer System Hardware Manual